Memory devices have storage capacities that are strongly linked to Moore's law, which states that the number of transistors on integrated circuits doubles approximately every 18 months. This rapid increase in storage capacity is due, in part, to a reduction in feature size for transistors and/or other devices on the memory devices. However, reduction in feature size is not the only factor leading to the increase in memory storage density. Another contributing factor is architectural changes made to the individual memory cells and/or the overall memory device. One architectural change is the movement from single bit memory cells (which each store a single bit of data, i.e., a “0” or a “1”) to multi-state memory cells (which are each capable of storing more than one bit of data).
Although multi-state memory cells potentially provide an increase in storage density for memory devices, it is more difficult to read data from a multi-state memory cell, relative to a single-bit memory cell. Traditional solutions require either large amounts of hardware or suffer from slow read times when interfacing with multi-state memory cells, and are therefore less than optimal. Therefore, the present disclosure provides for improved techniques for reading data from multi-state memory cells.